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Monday, April 8 • 5:25pm - 5:55pm
Adventures with RISC-V Vectors and LLVM

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RISC-V is a free and open instruction set architecture (ISA) with an established LLVM backend and numerous open-source and proprietary hardware implementations. The work-in-progress vector extension adds standardized vector processing, taking lessons both from traditional long-vector machines and from packed-SIMD approaches that dominated industrial designs in the past few decades. The resulting architecture aims to excel at various scales, from small embedded cores to large HPC accelerators and everything in between.

In this talk you will learn about the RISC-V vector ISA as well as LLVM support for it: vectorizing loops without needing scalar remainder handling, vectors whose length is not known at compile time, a vector unit that can be dynamically reconfigured for increased efficiency, and more.


Robin Kruppe

TU Darmstadt

Monday April 8, 2019 5:25pm - 5:55pm CEST